An integrated circuit includes internal circuitry which generates a digital output signal for transmission to other external circuits. In order to generate the requisite voltage on the output signal pins of the integrated circuit (IC), the IC is typically provided with one or more output buffers. The output buffer has large current driving capacity transistors which can drive a terminal or pad, connected to the output signal pin, to the requisite voltage (i.e., high or low) for conveying the correct logic value (i.e., logic `1` or logic `0`) of the output signal.
Recently, power reduction in ICs has become a priority. The most clear sign of this trend is the reduction of the standard power supply voltage VDD from 5 V to 3.3 V. In addition, there has also been a trend to reduce the power of a 12 V supply voltage to 5 V. With respect to the reduction 5 V to 3.3 V, since P=VI, a DC voltage reduction from 5 V to 3.3 V translates into a power savings of approximately forty percent (with 12 V to 5 V having a savings of approximately sixty percent). However, during the long anticipated transition period to completely convert from 5 V to 3.3 V, both 5 V and 3.3 V digital ICs will be used in system and board designs. For example, a systems memory may operate with a 3.3 V power supply but its monitor may require 5 V. Thus, a multi-voltage buffer is desired that can supply 5 V and 3.3 V signals as required.
FIG. 1 shows a conventional 3.3 V bidirectional (input/output) buffer circuit 10. Buffer circuit 10 comprises two stages; the input buffer stage 20 and the output buffer stage 30. Depending on the value of the Output Enable (OEN) control signal, the bidirectional buffer may act as an input buffer or as an output buffer. For example, when the OEN signal has a value of logic `1`, buffer circuit 10 acts as an input buffer, and when the OEN signal has a value of logic `0`, buffer circuit 10 acts as an output buffer. During the input phase, the driver transistors P1 and N1 are both off since the voltage levels at their respective gates are VDD and VSS, respectively. However, when a 5 V input signal is applied on pad 15, two conducting paths to the 3.3 V power supply will appear (as indicated by arrows 35 and 40). First, the parasitic diffusion diode Dl connected to the N-well of transistor P1 will open (become forward biased). Second, P1 itself will conduct current from pad 15 to the 3.3 V power source VDD since its gate-to-drain voltage is larger than its threshold voltage (in absolute value). Therefore, hazards, such as functional failure, may occur due to the loading value of the input signal and due to the reverse current in the power supply.
To eliminate the first conducting current path 40, the N-well of transistor P1 has to be tied to the 5 V power supply. However, the second conducting current path 35 remains. In addition, this arrangement results in other disadvantages including requiring dual power sources in the corresponding chip (e.g., 3.3 V/5 V or 5 V/12 V) and requiring an additional bonding pad for connecting the P1's N-well to the external power source.
FIG. 2 shows another conventional bidirectional buffer circuit as described in "5 V Compatibility with 3.3 V-Only CMOS ASICs", Microelectronics Journal, Vol 23, No. 8, 1992 by Henderson and Gal. Specifically, buffer circuit 50 includes a PMOS transistor Ti formed in an N-well that is connected to a 5 V power source 80 to avoid a forward biased condition on its parasitic diode. Furthermore, NMOS transistors T2 and T4/T5 reduce the stress voltage located at the drain of transistor T3 and at the gate of input buffer invertor 60, respectively. However, as with buffer circuit 10, the disadvantages of buffer circuit 50 include requiring dual power sources in the corresponding chip and requiring an additional bonding pad for connecting the P1's N-well to the external power source. Further, a leakage current flows at transistor Ti from pad 70 to the 3.3 V power source 90.
Another conventional buffer circuit is described in U.S. Pat. No. 5,300,835 to Assar et al. and is shown in FIG. 3. In buffer circuit 200, data DO and enable signal OEN* are first translated to voltage level NVDD by utilizing voltage translators. The voltage translator for signal DO comprises an invertor consisting of transistors 270 and 271 and cross wired transistors 266-269. The voltage translator for signal OEN* comprises an invertor consisting of transistors 276 and 277 and cross-wired transistors 272-275. Accordingly, PMOS driver transistor 250 can be completely off even when a high input signal, having a voltage level at NVDD, is applied to the pad. Although, unlike buffer circuit 10, the conducting current paths are eliminated, the buffer circuit 200 requires at least two power sources which require additional chip real estate for the supplemental power lines, bonding pad and connecting pins.
FIG. 4 is a further conventional bidirectional buffer circuit which is disclosed in "A 3/5 V Compatible I/O Buffer", IEEE Journal of Solid-State Circuits, July 1995 by Pelgrom and Dijkmans. As described in the disclosure, buffer circuit 100 provides the advantages of having a single power source and a single bonding pad, while exhibiting no leakage current of transistor P1. Buffer circuit 100 is fabricated using a `floating N-well` circuit technique. That is, the PMOS transistors P1-P8 are formed in a floating N-well.
In operation, when buffer circuit 100 acts as an output buffer, the floating N-well is normally biased to 3.3 V to keep the diffusion diode (at each PMOS transistor's p-n junction) reverse biased. In this condition, control signal OEN is logic `0` and transistor P4 is turned-on to charge the floating N-well to 3.3 V (transistor N6 passes the logic `0` value to the gate of transistor P4). Conversely, when OEN is logic `1`, buffer circuit 100 acts as an input buffer. When a 5 V input is applied, the floating N-well is directly charged to (5 V-V.sub.diodedrop =4.3 V), where V.sub.diodedrop is the voltage drop of diode DI. When a 0 V input is applied, the voltage level of the floating N-well is discharged to (3.3+.vertline.Vt.vertline.) volts at PMOS transistor P6, where Vt is the threshold of transistor P6. Since the voltage level of the floating N-well is switched between two different values, buffer circuit 100 may induce latch-up. In addition, buffer circuit 100 is rather complex and requires a relatively large layout area.
It is therefore the object of the present invention to provide a simple circuit design for a bidirectional multi-voltage buffer.
A further object of the present invention is to minimize the leakage current between the bonding pad and the power source.
An additional object of the present invention is to design a bidirectional buffer having a single power source.
Another object of the present invention is to design a bidirectional buffer having a single bonding pad.
Yet a further object of the present invention is to minimize latch-up of a bidirectional buffer.
Yet an additional object of the present invention is to ensure that the buffer stress voltage (i.e., the AC stress) is less than the oxide breakdown voltage of a corresponding gate oxide.